Method for making a semiconductor package and semiconductor package with integrated circuit chips

ABSTRACT

Method of fabricating a semiconductor package and semiconductor package containing an integrated circuit chip having, on one front face, electrical connection regions, in which a first multilayer plate ( 2 ) comprising an assembly face ( 2   a ) is furnished with an adhesive layer ( 8 ) and which has through-holes ( 9 ); and a second plate ( 3 ) has a recess ( 13 ) made in one assembly face ( 3   a ) fastened to the assembly face of the first plate via the said adhesive layer; the said chip ( 4 ) being placed in the said recess in a position such that its front face is fastened to the assembly face of the first plate via the said adhesive layer and that its electrical connection regions are located facing the through-holes of this first plate, and the bottom of the recess of the said second plate bearing against the rear face of the chip opposite the front face.

[0001] The present invention relates to the field of packaging orencapsulating integrated circuit chips and the field of semiconductorpackages containing such chips.

[0002] The most common method of producing semiconductor packagescontaining integrated circuit chips consists in fastening the chip to asupport member equipped with external or internal electrical connectionlines, for example a plate or a gate, and in encapsulating the chip andin part the support and electrical connection member in an encapsulationmaterial by injection moulding. According to a less common technique,the encapsulation material is replaced by a lid enveloping the chip at adistance and installed after fastening the chip to the support andelectrical connection member.

[0003] Although giving satisfaction for most of the time, thesetechniques require the implementation of expensive tools and ofrelatively lengthy fabrication steps. These semiconductor packagesproduced sometimes have weaknesses particularly with regard to theirmechanical strength or with regard to their resistance to corrosion,leading to a deterioration of the electrical connection pads of thechips and of the electrical connection means between these pads and theexterior of the packages. Furthermore, the known packages fabricatedespecially by injection use relatively expensive materials.

[0004] The aim of the present invention is in particular to solve, atleast partially, the problems mentioned above.

[0005] The subject of the present invention is firstly a method offabricating a semiconductor package containing an integrated circuitchip having, on one assembly face, electrical connection regions.

[0006] According to the invention, this method consists: in taking afirst multilayer plate, one assembly face of which is coated with anadhesive layer which can be activated and in producing through-holesthrough this plate, geometrically distributed depending on thedistribution of the said electrical connection regions of the chip; intaking a second plate and in producing a recess in one assembly face ofthis second plate capable of receiving the said chip; in placing thesaid chip on the said assembly face of the said first plate in aposition such that the aforementioned electrical connection regions ofthe chip are facing the said holes of this first plate and the saidassembly face of the said second plate on the said assembly face of thesaid first plate, the said chip being engaged in the said recess; and inexerting a pressure in the direction in which the said plates cometogether so that the said chip is sandwiched between the assembly faceof the said first plate and the bottom of the recess of the said secondplate and that the said adhesive layer is compressed between the saidassembly faces of the said plates and between the assembly face of thesaid first plate and the assembly face of the chip, such that the saidplates are fastened by activating the said adhesive layer.

[0007] According to the invention, subsequently, the method consists,preferably, in filling at least partially the said holes of the saidfirst plate with an electrical connection material.

[0008] According to the invention, the method may consist in placing, onthe said assembly face of the said first plate, the said chip then thesaid second plate by engaging the chip in the recess of the secondplate.

[0009] According to the invention, the method may consist in adhesivelyfastening the chip in the recess of the second plate then in placingthis second plate furnished with the chip on the said assembly face ofthe said first plate.

[0010] According to the invention, the method preferably consists infurnishing the electrical connection regions of the chip with projectingelectrical connection pads, these electrical connection pads beingengaged in the holes of the first plate while it is being assembled.

[0011] According to the invention, the method preferably consists infilling the said holes of the first plate with an electrical connectionmaterial so as to produce projecting electrical connection pads on theface of the said first plate opposite its assembly face.

[0012] The subject of the present invention is also a semiconductorpackage containing an integrated circuit chip having, on one front face,electrical connection regions.

[0013] According to the invention, this package comprises: a firstmultilayer plate, one assembly face of which is furnished with anadhesive layer and which has through-holes; and a second plate which hasa recess made in one assembly face fastened to the assembly face of thefirst plate via the said adhesive layer; the said chip being placed inthe said recess in a position such that its front face is fastened tothe assembly face of the first plate via the said adhesive layer andthat its electrical connection regions are located facing thethrough-holes of this first plate, and the bottom of the recess of thesaid second plate bearing against the rear face of the chip opposite thefront face.

[0014] According to the invention, the holes of the said first plate arepreferably filled with an electrical connection material producingprojecting electrical connection pads on the face of this first plateopposite its assembly face.

[0015] According to the invention, the said first plate preferablycomprises an outer layer opposite its assembly face made of a materialforming a moisture barrier, in particular made of Teflon or of afluoropolymer.

[0016] According to the invention, the said first plate preferablycomprises an interlayer made of a plastic, in particular made of athermoplastic or made of a liquid crystal polymer LCP.

[0017] According to the invention, the said second plate preferablycomprises an outer layer opposite its assembly face made of a materialforming a moisture barrier, in particular made of Teflon or of afluoropolymer.

[0018] According to the invention, the said second plate preferablycomprises an interlayer made of a plastic, in particular made of athermoplastic or made of a liquid crystal polymer (LCP).

[0019] According to the invention, the assembly face of the said secondplate is preferably furnished with an adhesive layer.

[0020] According to the invention, an adhesive layer is preferablyinserted between the bottom of the recess of the said second plate andthe rear face of the chip.

[0021] According to the invention, the package may advantageouslycomprise a heat sink block passing through an opening in the said secondplate and having one face fastened bearing against the rear face of thechip.

[0022] The present invention will be better understood on studying asemiconductor package containing an integrated circuit chip and a methodof fabricating this package, described by way of non-limiting examplesand illustrated by the drawing in which:

[0023]FIG. 1 shows a transverse section of a first plate of theaforementioned package, in a position corresponding to a firstfabrication step of this package;

[0024]FIG. 2 shows a top view of the first plate of FIG. 1;

[0025]FIG. 3 shows a transverse section of the aforementioned firstplate, furnished with an integrated circuit chip, in positionscorresponding to a second fabrication step of the package;

[0026]FIG. 4 shows a transverse section of the aforementioned firstplate furnished with the integrated circuit chip and with a secondplate, in positions corresponding to a third fabrication step of theaforementioned package;

[0027]FIG. 5 shows, in transverse section, a final semiconductor packageaccording to the present invention, after a fourth fabrication step;

[0028]FIG. 6 shows, in transverse section, a variant embodiment of theaforementioned semiconductor package, after a fifth fabrication step.

[0029] With reference to FIGS. 1 to 5, the various fabrication steps ofa semiconductor package 1 will be described.

[0030] This semiconductor package 1 comprises a first plate 2 which hasan assembly face 2 a, a second plate 3 which has an assembly face 3 a,and an integrated circuit chip 4 which has an assembly face 4 a on whicha multiplicity of electrical connection regions 5 is distributed.

[0031] The first plate 2 is prefabricated so as to have a stiff innerlayer 6 made of a plastic preferably having a melting point greater than300° C., for example made of a thermoplastic or made of a liquid crystalpolymer (LCP), one face of which is coated with a layer 7 forming amoisture barrier, for example made of a Teflon or a fluoropolymer, andthe other face of which is coated with an insulating adhesive layer 8which can be activated forming the assembly face 2 a.

[0032] The first plate 2 has a multiplicity of through-passages 9 whichare distributed so as to correspond to the geometrical distribution ofelectrical connection regions 5 of the chip 4 as is shown morespecifically in FIG. 2.

[0033] As is shown in FIG. 1, a fabrication step consists in placing thefirst plate 2 thus constituted on a table 10 of a machine, furnishedwith conventional means for holding the plate 2, for example by suction,the outer layer 7 being placed in contact with the table 10. Thisoperation can be carried out by a pick-and-press head 11 of the machine,shown in FIG. 4.

[0034] As is shown in FIG. 3, the electrical connection regions 5 of thechip 4 are furnished in advance with projecting electrical connectionpads 12.

[0035] A following fabrication step consists in placing the chip 4 onthe first plate 2 in a position such that its assembly face 4 a bearsagainst the assembly face 2 a of the first plate 2, on its adhesivelayer 8, and that the electrical connection pads 12 engage in thethrough-holes 9 corresponding to this plate. This operation isadvantageously carried out by the pick-and-press head 11.

[0036] The second plate. 3, which for example consists of a materialidentical to that of the interlayer 6 of the first plate 2, has, in itsassembly face 3, a recess 13 whose section parallel to its assembly face3 a is slightly above the section of the chip 4 parallel to its assemblyface 4 a and whose depth corresponds to the thickness of the chip 4.

[0037] As is shown in FIG. 5, a following fabrication step consists inplacing the second plate 3 of the first plate 2 by engaging the chip 4in the recess 13 such that in the final position, the bottom 13 a of therecess 13 bears against the rear face 4 b of the chip 4 and that itsassembly face 3 a surrounding the recess 13 bears against the assemblyface 2 a of the first plate 2. To carry out such an operation, thepick-and-press head 11 is advantageously used.

[0038] In a following fabrication step, the pick-and-press head 11 isheld on the second plate 3 and exerts a pressure towards the table 10 inthe direction in which the plates 2 and 3 come together, so that thechip is sandwiched between the assembly face 2 a of the first plate 2and the bottom 13 a of the recess 13 of the second plate 3.

[0039] Under the effect of the pressure exerted, the adhesive layer 8 ofthe first plate 2 is compressed over its entire surface by the assemblyface 4 a of the chip 4 and by the assembly face 2 a of the second plate3 and can be activated depending on its actual characteristics so as toform a sealed joint.

[0040] The adhesive layer 8 may in fact be chosen so as to be activatedsimply by exerting pressure, or by an external means, for exampleconsisting of a means of heating the table 10.

[0041] As is shown in FIG. 5, a following fabrication step consists infilling the holes 9 of the first plate 2 with an electrical connectionmaterial 14, merging with the material forming the pads 12 of the chip4, so as to form outer, preferably projecting, electrical connectionpads 15.

[0042] The semiconductor package 1 thus obtained especially has thefollowing advantages, which result mainly from the continuity of theadhesive layer 8 and from the fact that the chip 4 is completelyenclosed.

[0043] The adhesive layer 8 makes it possible to assemble the plates 2and 3 and the chip 4 and provides compensation for any differencesbetween the thickness of the chip 4 and the depth of the recess 13 ofthe second plate 3.

[0044] The adhesive layer 8 forms a continuous electrical insulation andsealing barrier with regard to electrical connection regions 5 andelectrical connection pads 12 extended by the electrical connection pads15, each from the others and from the outside of the package 1.

[0045] The outer layer 7 contributes to protecting the electricalconnection regions 5 and the electrical connection pads 12 extended bythe electrical connection pads 15.

[0046] The interlayer 6 of the first plate 2 and the second plate 3provide the stiffness for the package 1.

[0047] In a fabrication variant, the chip 4 could be previously fastenedin the recess 13 of the second plate 3, for example via an adhesivelayer inserted between the rear face 4 b of the chip 4 and the bottom 13a of the recess 13 and this assembly could be placed on the first plate2 arranged on the table 10 in order to be assembled to the latter asdescribed with reference to FIG. 4.

[0048] In a structural variant, the second plate 3 could be equivalentto the first plate 2 and have an interlayer made of a plastic such as athermoplastic or made of a liquid crystal polymer (LCP), an outer layerprotecting against moisture and an inner adhesive layer on its assemblyface 2 a.

[0049] In a further alternative embodiment shown in FIG. 6, the secondplate 3 has an opening 16 opening out into the bottom 13 a of the recess13, a sealed annular adhesive layer 17 then preferably being insertedbetween the chip and the wall of the recess 13 of this second plate 3.

[0050] Thus, a heat sink unit 18 can subsequently be mounted on thepackage 1 by engaging a part 19 of this unit 18 through the opening 16,this part 19 being, for example, fastened flat against the rear face 4 bof the chip 4 by a layer of hot-melt adhesive.

[0051] The present invention is not limited to the examples describedabove. Many other alternative embodiments are possible without departingfrom the scope defined by the appended claims.

1. Method of fabricating a semiconductor package containing anintegrated circuit chip having, on one assembly face, electricalconnection regions, characterized in that it consists: in taking a firstmultilayer plate (2), one assembly face (2 a) of which is coated with anadhesive layer (8) which can be activated and in producing through-holes(9) through this plate, geometrically distributed depending on thedistribution of the said electrical connection regions (5) of the chip(4); in taking a second plate (3) and in producing a recess (13) in oneassembly face (3 a) of this second plate capable of receiving the saidchip (4); in placing the said chip (4) on the said assembly face of thesaid first plate (2) in a position such that the aforementionedelectrical connection regions (5) of the chip are facing the said holes(9) of this first plate and the said assembly face of the said secondplate (3) on the said assembly face of the said first plate (2), thesaid chip being engaged in the said recess (13); and in exerting apressure in the direction in which the said plates come together so thatthe said chip is sandwiched between the assembly face of the said firstplate and the bottom of the recess of the said second plate and that thesaid adhesive layer is compressed between the said assembly faces of thesaid plates and between the assembly face of the said first plate andthe assembly face of the chip, such that the said plates are fastened byactivating the said adhesive layer.
 2. Method according to claim 1,characterized in that it subsequently consists in filling at leastpartially the said holes (9) of the said first plate (2) with anelectrical connection material (14).
 3. Method according to either ofclaims 1 and 2, characterized in that it consists in placing, on thesaid assembly face of the said first plate (2), the said chip (4) thenthe said second plate (3) by engaging the chip in the recess (13) ofthis second plate.
 4. Method according to either of claims 1 and 2,characterized in that it consists in adhesively fastening the chip (4)in the recess (13) of the second plate (3) then in placing this secondplate furnished with the chip on the said assembly face of the saidfirst plate (2).
 5. Method according to any one of the preceding claims,characterized in that it consists in furnishing the electricalconnection regions (5) of the chip with projecting electrical connectionpads (12), these electrical connection pads being engaged in the holes(13) of the first plate (2) while it is being assembled.
 6. Methodaccording to any one of the preceding claims, characterized in that itconsists in filling the said holes (9) of the first plate with anelectrical connection material so as to produce projecting electricalconnection pads (15) on the face of the said first plate (2) oppositeits assembly face (2 a).
 7. Semiconductor package containing anintegrated circuit chip having, on one front face, electrical connectionregions, characterized in that it comprises: a first multilayer plate(2), one assembly face (2 a) of which is furnished with an adhesivelayer (8) and which has through-holes (9); and a second plate (3) whichhas a recess (13) made in one assembly face (3 a) fastened to theassembly face of the first plate via the said adhesive layer; the saidchip (4) being placed in the said recess in a position such that itsfront face is fastened to the assembly face of the first plate via thesaid adhesive layer and that its electrical connection regions arelocated facing the through-holes of this first plate, and the bottom ofthe recess of the said second plate bearing against the rear face of thechip opposite the front face.
 8. Package according to claim 7,characterized in that the holes (9) of the said first plate (2) arefilled with an electrical connection material (14) producing projectingelectrical connection pads (15) on the face of this first plate oppositeits assembly face.
 9. Package according to either of claims 7 and 8,characterized in that the said first plate (2) comprises an outer layer(7) opposite its assembly face (2 a) made of a material forming amoisture barrier, in particular made of Teflon or made of afluoropolymer.
 10. Package according to any one of claims 7 to 9,characterized in that the said first plate (2) comprises an interlayer(6) made of a plastic, in particular made of a thermoplastic or made ofa liquid crystal polymer (LCP).
 11. Package according to any one ofclaims 7 to 10, characterized in that the said second plate (3)comprises an outer layer opposite its assembly face made of a materialforming a moisture barrier, in particular made of Teflon or of afluoropolymer.
 12. Package according to any one of claims 7 to 11,characterized in that the said second plate (3) comprises an interlayermade of a plastic, in particular made of a thermoplastic or made of aliquid crystal polymer (LCP).
 13. Package according to any one of claims7 to 12, characterized in that the assembly face (3 a) of the saidsecond plate (3) is furnished with an adhesive layer.
 14. Packageaccording to any one of claims 7 to 13, characterized in that itcomprises an adhesive layer (17) between the bottom of the recess (13)of the said second plate (2) and the rear face of the chip (4). 15.Package according to any one of claims 7 to 14, characterized in that itcomprises a heat sink unit (18) passing through an opening (16) in thesaid second plate (3) and having one face fastened bearing against therear face of the chip.